Who am I

Foto Màrius My name is Marius Monton. I have a PhD in Computer Science by the Universitat Autonoma de Barcelona (UAB) and Masters in Microelectronics and Electronic Systems and Computer Engineer degree from the same university. I’m co-founder at IoT Partners, engineering and consultancy focused on Internet of Things.
Previously I was working as Head of Innovation  in WorldSensing. Before that, I worked as Firmware engineer in the same company. I was working several years as engineer at Cephis-UAB. He also worked as associate professor at the university. In addition, I’m  working as consultor for GreenSocs developing TLM-2.0 based solutions for ESL businesses. Projects done with GreenSocs:

  • Implementation of SystemC Bridge for Simics (Virtutech).
  • Add support to checkpoint & restore to SystemC and the integration into   SystemC Bridge by Simics.
  • SoC  modelling using SystemC with QEMU as ISS (link).

My PhD Slides

[slideshare id=6253011&doc=presentaciophd-101220042157-phpapp01]

And here my thesis (PDF).
My current projects are:
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1 Comment

  1. Janos VEGH
    Posted Tuesday, 25 December 2018 at %I:%M %p | Permalink

    Dear Marius,
    I have just found your RISC-V SystemC simulator and I want to know whether you are interested in a very challenging project. I want to submit in January a FET-Open project for elaborating principles of a new computing paradigm and some details of electronic implementation.
    All present processors (including RISCV) are implemented in single-processor approach, which has its performance limitations, and those limitations strongly limit their utilization performance in many-processor systems. My idea is to extend Neumann’s paradigm to many processors. I have a SystemC RTL(hybrid) simulator with Y86 cores (this enlightens adding new instruction types and registers) which works and shows the advantages of the approach.
    Anyhow, I want to continue and I want to use elements of your implementation in the future, because of the popularity of RISCV and because I want to go to TLM level.
    If you are interested, I can send some details.
    My simulator works much similar to yours: the execution of the Y86 instruction is simulated on ISA level, with simulating the execution time. However, the cooperation of the cores is simulated (nearly) in a cycle accurate way, using event-driven operation.
    Your work would be to convert the simulator from Y86 cores to RISCV cores, as well as to convert RISCV from segregated processor to multicore-aware one.

    Best regards

    Janos

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