CV

Personal Details

Name: Màrius Montón i Macián
Age & DOB: 3, July 28th, 1976
Sex: Male
Nationality: Spanish
Address: Barcelona. SPAIN

Education

  • Ph. D. In Computer Science, Universitat Autònoma de Barcelona (UAB), 2010.
    • Dissertation: Checkpointing for Virtual Platforms and SystemC-TLM-2.0.
  • M.S. in Microelectronics, Universitat Autònoma de Barcelona (UAB), 2006.
    • Master Thesis: Platform based design: Intellectual property models
  • Computer Science Engineering, Universitat Autònoma de Barcelona (UAB), 2003.

Language skills

  • Catalan: native
  • Spanish: native
  • English: conversational

Professional experience

  • Innovation Unit Manager at Worldsensing, 2012 –
    • EU Projects
    • Innovation process management
  • R&D Engineer Worldsensing 2010 – 2012
    • Firmware Engineer: FreeRTOS
  • R&D Engineer at CEPHIS (http://cephis.uab.cat), 2005 . 2010.
    • Involved in several R&D projects
    • TI Manager
    • Intellectual Property Manager
  • Freelance engineer for GreenSocs (http://www.greensocs.com), 2007 . 2010.
    • Implementation of the SystemC Bridge for Simics by Virtutech.
    • Add support to checkpoint & restore to SystemC integrated into Simics SystemC Bridge
    • Complete SoC modeled in SystemC using QEMU as a ISS.
  • Assistant teacher, Universitat Autonoma de Barcelona (UAB), 2003 . 2014:
    • Computers Basics, 1st semesters Computer Science Engineering.
    • Digital Systems Technologies, 7th semester Computer Science Engineering.
    • HW/SW Co-design. 7th semester Computer Science Engineering.
    • Electronic Systems Design, 8th semester Electronic Engineering.
    • Some lectures on gPlatforms based designh and gSystemCh for Master and PhD students.
    • >15 Final Degree Projects directed
  • Assistant teacher, Universitat OBerta de Catalunya (UOC), 2012 – 2014:
    • Embedded Systems, Computer Science Engineer.

Research skills

  • QEMU-SC and QBox Virtual platforms founder and developer.
  • Extensive knowledge of SystemC and TLM-2, VHDL and Synthesis tools for FPGA.
  • C and C++ expertise, among Java, PHP and other programming languages.

Publications

Journals

  1. Màrius Monton, Jakob Engblom, Mark Burton, “Checkpointing for Virtual Platforms and SystemC-TLM”, In IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  Volume PP, Issue: 99, Pages:1-9. DOI: dx.doi.org/10.1109/TVLSI.2011.2181881

Book chapters

  1. M. Montón, J. Engblom, C. Schröder, J. Carrabina and M. Burton, “Checkpoint and Restore for Systemc Models”, In Bornione D., editor. Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s, Vol 63. Springer 2010; (Lecture Notes on Electrical Engineering; vol 63). ISBN: 978-9048193035.
  2. Casanovas, P.; Binefa, X.; Gracia, C.; Montón, M.; Carrabina, J.; Serrano, J.; Blázquez, M.; López-Cobo, J.M.; Teodoro, E.; Galera, N.; Poblet, M., “The e-Sentencias prototype. Developing ontologies for legal multimedia applications in the Spanish Civil Courts”. In Casanovas, P.; Breuker, J.; Klein, M.; Francesconi, E. (eds) Channeling the legal informational flood. Legal Ontologies and the Semantic Web. IOS Press, 2009, 188, 199-219.

Conference papers

  1. Marius Monton, Mark Burton and Frederic Konrad; GreenSocs David Black presenting, “Reverse Execution for Qemu-Based SystemC Virtual Platforms” 19th NASCUG, June 2013
  2. M. Montón, J. Engblom, M. Burton, “Checkpoint and Restore for SystemC Models” in Proceedings of International Forum on Specification and Design Languages (FDL), Sophia Antipolis, France, Sep. 2009, pp. 1-6.
  3. M. Montón, J. Carrabina, M. Burton, “Mixed Simulation Kernels for High Performance Virtual Platforms”, in Proceedings of International Forum on Specification and Design Languages (FDL), Sophia Antipolis, France, Sep. 2009, pp. 1-6.
  4. M. Montón, B. Martínez, J. Carrabina, “Síntesis de Canales TLM para procesador Nios-II” in VIII Jornadas de Computación Reconfigurable y Aplicaciones, (JCRA), Madrid, Sep., 2008.
  5. B. Martínez, J. López, M. Montón, J. Carrabina, “Sistema de Control Acceso por Reconocimiento Óptico de Documentos sobre Nios-II”, in VIII Jornadas de Computación Reconfigurable y Aplicaciones, (JCRA), Madrid, Sep., 2008.
  6. P. Rujan, F. Vuillod, B. Gomm, M. Montón, D. Castells. “AMASS Core: Associative Memory Array for Semantic Search” in IP Based Electronic System Conference & Exhibition. Dec. 2007. Grenoble, France.
  7. C. Gracia, P. Casanovas, J. Carrabina, X. Binefa, E. Teodoro, M. Montón, N. Casellas, C. Montero, N. Galera, J. Serrano, M. Poblet, “Legal Knowledge Acquisition and Multimedia Applications”, in Knowledge acquisition from multimedia content Workshop (KAMC’07). Second International Conference on Semantic and Digital Media Technologies, SAMT 2007, Genova, Italy, Dec., 2007.
  8. M. Montón, J. Carrabina, C. Montero, J. Serrano, X. Binefa, C. Gracia, M. Blázquez, J. Contreras, E. Teodoro, N. Casell, J.J. Vallbé, M. Poblet and P. Casanovas, “Accelerating Semantic Search with Application of Specific Platform” in Workshop on Semantic Web Technology for Law (SW4Law), Stanford University, USA, June, 2007.
  9. X. Binefa, C. Gracia, M. Montón, J. Carrabina, C. Montero, J. Serrano, M. Blázquez, R. Benjamins, E. Teodoro, P. Casanova, M. Poblet, “Developing ontologies for legal multimedia applications”, in Legal Ontologies and Artificial Intelligence Technique (LOAIT Workshop), Stanford University, USA, 2007.
  10. M. Montón, A. Portero, M. Moreno, B. Martínez, J. Carrabina, “Mixed SW/SystemC SoC Emulation Framework” in Proceedings of IEEE International Symposium on Industrial Electronics. (ISIE). Vigo, June 2007, pp. 2338-2341.
  11. A. Portero, G. Talavera, M. Montón, B. Martinez, J. Carrabina, “NoC System for MPEG-4 SP using heterogeneous tiles”, in XXI Conference on Design of Circuits and Integrated Systems. (DCIS), Barcelona 22-24 November 2006.
  12. A. Portero, G. Talavera, M. Montón, B. Martinez, M. Moreno, F. Cathoor, J. Carrabina, “Energy-aware MPEG-4 Single Profile in HW-SW Multi-platform implementation”, in IEEE International SOC Conference, Sep., 2006, pp 1316..
  13. B. Martínez, M. Montón, J. Carrabina, “Síntesis de Unidades Funcionales para Soft-Cores desde un modelo C/C++”, in VI Jornadas de Computación Reconfigurable y Aplicaciones, (JCRA), Càceres, Sep., 2006.
  14. A. Portero, G. Talavera, M. Montón, B. Martinez, F. Cathoor, J. Carrabina, “Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation”, in Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, USA: IEEE Computer Society, 2006, pp. 257-260
  15. L. Ribas-Xirgo, D. Castells, M. Monton, J. Carrabina, “A Rapid Sorting Unit based on Programmable Shifting Register Files”, in XX Conference on Design of Circuits and Integrated Systems. (DCIS), Lisboa, Portugal, Nov., 2005.
  16. M. Montón, O. Font, J. Joven, P. García, L. Terés, J. Carrabina, “XML specification and tools for Automatic SoC Generation”, in XIX Conference on Design of Circuits and Integrated Systems. (DCIS), Bordeaux, France, Nov., 2004.
  17. D. Castells, M. Montón, R. Pla, D. Novo, A. Portero, O. Navas, J. Farré, L. Ribas, J. Carrabina, “Comparing Design Flows for Structural System Level Specifications facing FPGA Platforms”, in XIX Conference on Design of Circuits and Integrated Systems. (DCIS), Bordeaux, France, Nov., 2004. .
  18. D. Castells-Rufas, M. Montón, L. Ribas, J. Carrabina, “High performance Parallel Llinear Sorter Core Design”, in GSPx, The international embedded Solutions Event, Santa Clara, CA, Sep., 2004.
  19. J. Carrabina, M. Montón, R. Martínez, J. Joven, O. Font, R. Ruíz, P. García, L. Terés, “Bus-centric SoC Architecture Generation Tools”, in GSPx, The international embedded Solutions Event, Santa Clara, CA, Sep., 2004.

Teaching publications

  1. X. Fitó, G. Talavera, B. Lorente, M. Montón, B. Martínez, C. Ferrer, E. Valderrama, “Cas pràctic d’adaptació metodològica a les directrius EEES d’una assignatura d’enginyeria Informàtica”, in III Jornada de Campus d’Innovació Docent, UAB, Barcelona, Spain, 2006.
  2. G. Talavera, X. Fitó, B. Lorente, A. Portero, M. Montón , B. Martínez, J. Oliver, C. Ferrer, L. Ribas, J. Aguiló, E. Valderrama, “Adaptación metodológica a las nuevas directrices del EEES en la enseñanza tècnica universitaria”, in Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE), Madrid, Spain, 2006.
  3. G. Talavera, B. Lorente, M. Montón , B. Martínez, J. Oliver, C. Ferrer, L. Ribas, J. Aguiló, E. Valderrama, “Nuevas metodologías docentes y autoaprendizaje en la enseñanza técnica universitaria”, in IV Congrès Internacional de Docència Universitària i Innovació. (CIDUI), Barcelona, Spain, 2006.

R&D Projects

  1. Transmedia, 2009SGR700, PR: Pilar Orero; Budget: 36,000 €.
  2. Diseño de una plataforma MP para Inteligencia Ambiental, TEC2008-03835. PR: Jordi Carrabina; Budget: 83,974,00 €.
  3. IP Core and System Design of Associative Memory Arrays for Semantic Search. AMASS. CRAFT 18283/AMASS. PR: Jordi Carrabina; Budget: 209.680,00 €.
  4. Many other Spanish government and private fund projects.

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